1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation, and then a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to the gate on which sidewall spacers have been formed. The spacers are typically oxides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics.
Complementary metal-oxide semiconductor (CMOS) circuits include N-channel (NMOS) devices and P-channel (PMOS) devices. Conventional processes typically use N-well masks and P-well masks early in the processing sequence to define the NMOS and PMOS regions. Conventional processes also typically include a single masking step for forming the gates for the NMOS and PMOS devices, separate masking steps for implanting lightly doped N-type source/drain regions into the NMOS device and lightly doped P-type source/drain regions into the PMOS device, formation of spacers adjacent to the gates of the NMOS and PMOS devices, and then separate masking steps for implanting heavily doped N-type source/drain regions into the NMOS device and heavily doped P-type source/drain regions into the PMOS device. The N-type dopant used to dope the NMOS source/drain
regions is typically arsenic or phosphorus, and P-type dopant used to dope the PMOS source/drain regions is typically boron.
Ion implantation damages the substrate material. During implantation, the dopant ions collide with atoms in the substrate and displace large amounts of such atoms from their lattice sites. In addition, the implanted dopant generally fails to occupy substitutional sites and therefore is not electrically activated. Accordingly, after the dopant is implanted into the source/drain regions, the drive-in step is applied to reduce crystalline damage by annealing the substrate and to activate the dopant by shifing the dopant into substitutional sites. The drive-in step also diffuses the dopant to depths beyond the range of implantation damage. Since present demands for shallow junctions do not allow for extensive dopant redistribution, the drive-in step is usually a rapid thermal anneal.
The diffusion characteristics of various dopants in semiconductor substrates is a complex phenomena which depends, in part, on dopant concentration, substrate (background) doping, junction depth, temperature, and the atmosphere. Unfortunately, at a given high temperature, boron tends to diffuse into the semiconductor substrate at a far greater rate than arsenic or phosphorus. For instance, at 1000.degree. C., boron generally diffuses into silicon at least ten times faster than arsenic or phosphorus. This is partly due to the fact that the activation energy of boron (and consequently the height of the energy barrier that boron must overcome to move within the silicon lattice) is lower than that of arsenic or phosphorus. If, for instance, the gates over the NMOS and PMOS regions have similar lengths, then the effective channel length of the NMOS device may be significantly greater than the effective channel length of the PMOS device due to the rapid diffusion of boron. The problem has been alleviated by implanting the lightly doped source/drain regions for the NMOS and PMOS devices and the heavily doped source/drain regions for the NMOS device, performing a first drive-in step using a first rapid thermal anneal at a first temperature, implanting the heavily doped source/drain regions for the PMOS device, and performing a second drive-in step using a second rapid thermal anneal at a second temperature lower than the first temperature. In this manner, the heavily doped source/drain regions for the PMOS device need not be subjected to the first temperature, however, the lightly doped source/drain regions for the PMOS device are still subjected to the first temperature.
Accordingly, a need exists for an improved method of making N-channel and P-channel devices in which the diffusion of the P-type dopant, such as boron, is reduced with respect to the N-type dopant.